The present invention relates to spread spectrum clock generators generally and, more particularly, to a circuit and method for linear control of a spread spectrum transition.
Electronic devices must meet maximum electromagnetic interference (EMI) radiation limits as specified by the U.S. FCC and other comparable regulatory agencies in other countries. Since new FCC requirements call for PC motherboards to be able to pass EMI tests xe2x80x9copen box,xe2x80x9d manufacturers will not be able to rely on the shielding provided by the case in meeting EMI requirements.
An EMI suppression-enabled clock IC can reduce the system radiated EMI. The reduction in radiated EMI can result in dramatic cost savings for the system. Conventional techniques for reducing EMI include ground planes, filtering components, shielding, and spread spectrum modulated system clocks.
In the spread spectrum technique, instead of concentrating all of a frequency reference""s energy on a single frequency, the energy is spread out by modulating the frequency. The modulation results in the energy being spread over a frequency range, instead of being concentrated on one particular frequency. Since the FCC and other regulatory bodies are concerned with peak emissions, not average emissions, the reduction in peak energy due to spread spectrum modulation will help a product meet FCC requirements.
One type of spread spectrum modulation is center modulation (e.g., +/xe2x88x92). A center modulated clock provides the same system processing performance as for a CPU using a non-modulated clock. However, system designers are concerned about overboosting processors. If a processor designed for a 100 MHz reference is used with a reference that spends most of the time at 100.5 MHz, the processor will be operating at a higher than rated speed during that period of time. To alleviate this concern, modulation can be specified as xe2x80x9cdown only,xe2x80x9d e.g., xe2x88x920.5%. A xe2x88x920.5% modulation, in the same 100 MHz example, would vary the frequency from 99.5 to 100 MHz. This is achieved by moving the center frequency down. What is specified as xe2x80x9c100 MHz, with xe2x88x920.5% modulationxe2x80x9d can really be thought of as xe2x80x9c99.75 MHz with +/xe2x88x920.25% modulation.xe2x80x9d Using xe2x80x9cdown onlyxe2x80x9d modulation results in a performance degradation of a CPU, as the nominal 100 MHz signal is now less than 100 MHz.
If the spread spectrum clock generator could be configured for the spread spectrum modulation to be switched on and off, a system could have reduced EMI while still providing top performance when needed. However, during the transition period when the spread spectrum modulation is switching on, the frequency can change faster than the internal clock of the CPU can track. When the slew rate is too high (i.e., the frequency changes too fast), the CPU will lose track of the input clock and hang.
Referring to FIG. 1, a block diagram of a circuit 10 illustrating a conventional phase lock loop based spread spectrum clock generator is shown. The circuit 10 generates a signal OUT in response to (i) a reference signal REF and a command signal SSON. The signal REF is presented to an input prescaler 12 and a multiplexer 14. The signal OUT is presented to a feedback prescaler 20 and a multiplexer 22. The signal SSON is presented to the control inputs 28 and 30 of the multiplexers 14 and 22, respectively and an input 32 of the spread spectrum circuitry 26. In response to the command signal SSON, (i) the multiplexer 14 selects between the reference signal REF and an output of the input prescaler 12, (ii) the multiplexer 22 selects between the output signal OUT and an output of the feedback prescaler 20, and (iii) the spread spectrum circuitry 26 switches on and/or switches off spread spectrum modulation.
Referring to FIG. 2, a numerical simulation and an oscilloscope tracing illustrating the signal OUT are shown. A portion 40a of the numerical simulation and a portion 40b of the oscilloscope tracing illustrate the high slew rate of the transient response of the circuit 10 when spread spectrum modulation is switched on.
The present invention concerns a spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.
The objects, features and advantages of the present invention include providing a circuit and method for linear control of a spread spectrum transition that may (i) provide a slow rate of frequency change during spread spectrum turn-on and/or (ii) provide a linear control of the frequency change during spread spectrum turn-on.